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1 ?2016 integrated device technology, inc. october 20, 2016 description the 8P34S2106 is a high-performance, low-power, differential dual 1:6 lvds output 1.8v fanout buffer. the device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. two independent buffer channels are available, each channel has six low skew outputs. high isolation between channels minimizes noise coupling. ac characteristics such as propagation delay are matched between channels. guaranteed output-to-ou tput and part-to-part skew characteristics make the 8P34S2106 ideal for those clock distribution applications demanding we ll-defined performance and repeatability. the device is charac terized to operate from a 1.8v power supply. the integrated bias voltage references enable easy interfacing of ac-coupled signals to the device inputs. block diagram features ? dual 1:6 low skew, low additive jitter lvds fanout buffers ? matched ac characteristics across both channels ? high isolation between channels ? low power consumption ? both differential clka, nclka and clkb, nclkb inputs accept lvds, lvpecl and single-ended lvcmos levels ? maximum input clock frequency: 2ghz ? output amplitudes: 350mv, 500mv (selectable) ? output bank skew: 10ps typical ? output skew: 20ps typical ? low additive phase jitter, rms: 45fs typical (f ref = 156.25mhz, 12khz - 20mhz) ? full 1.8v supply voltage mode ? device current consumption (i dd ): 210ma typical ? lead-free (rohs 6), 40-lead vfqfn packaging ? -40c to 85c ambient operating temperature ? supports case temperature up to 105c 8p34s2104 transistor count: clka nclka vrefa selaa voltage reference a qa0 nqa0 qa1 nqa1 qa2 nqa2 qa3 nqa3 qa4 nqa4 qa5 nqa5 51k 51k 51k clkb nclkb vrefb selab voltage reference b 51k 51k 51k qb0 nqb0 qb1 nqb1 qb2 nqb2 qb3 nqb3 qb4 nqb4 qb5 nqb5 vdda 51k 51k vdda vddb vddb 8P34S2106 transistor count: 1113 8P34S2106 datasheet dual 1:6 lvds output 1.8v fanout buffer
2 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet pin assignments figure 1. pin assignments for 6mm x 6mm vfqfn package ? top view pin descriptions table 1. pin descriptions [a] number name type description 1 selab input [pu] control input. output amplitude select for channel b. 2 clkb input [pd] non-inverting differential clock/data input for channel b. 3 nclkb input [pd/pu] inverting differential clock/data input for channel b. 4 vrefb output bias voltage reference for the clkb, nclkb input pairs. 5v ddb power power supply pin for the core and inputs of channel b. 6v dda power power supply pin for the core and inputs of channel a. 7 vrefa output bias voltage reference for the clka, nclka input pairs. 8 nclka input [pd/pu inverting differential clock/data input for channel a. 9 clka input [pd] non-inverting differential clock/data input for channel a. 10 selaa input [pu] control input. output amplitude select for channel a. 11 v ddqa power power supply pin for the channel a outputs qa[0:5] 12 qa0 output differential output pair a0. lvds interface levels. 13 nqa0 output differential output pair a0. lvds interface levels. 14 qa1 output differential output pair a1. lvds interface levels. 15 nqa1 output differential output pair a1. lvds interface levels. 16 qa2 output differential output pair a2. lvds interface levels. 8P34S2106 11 12 13 14 15 16 17 18 19 20 31 32 33 34 35 36 37 38 39 40 21 22 23 24 25 26 27 28 29 30 12345678910 nclkb vrefb v ddb clkb selab v dda vrefa nclka clka selaa qa2 nqa1 qa1 qa0 v ddqa nqa0 nqa2 qa3 nqa3 v ddqa qa4 qb0 nqb0 gnd nqa4 qa5 nqa5 qb1 nqb1 gnd qb3 qb2 nqb2 qb4 nqb3 nqb4 qb5 nqb5 v ddqb v ddqb
3 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet 17 nqa2 output differential output pair a2. lvds interface levels. 18 qa3 output differential output pair a3. lvds interface levels. 19 nqa3 output differential output pair a3. lvds interface levels. 20 v ddqa power power supply pin for the channel a outputs qa[0:5] 21 gnd power power supply ground. 22 qa4 output differential output pair a4. lvds interface levels. 23 nqa4 output differential output pair a4. lvds interface levels. 24 qa5 output differential output pair a5. lvds interface levels. 25 nqa5 output differential output pair a5. lvds interface levels. 26 qb0 output differential output pair b0. lvds interface levels. 27 nqb0 output differential output pair b0. lvds interface levels. 28 qb1 output differential output pair b1. lvds interface levels. 29 nqb1 output differential output pair b1. lvds interface levels. 30 gnd power power supply ground. 31 v ddqb power power supply pin for the channel b outputs qb[0:5]. 32 qb2 output differential output pair b2. lvds interface levels. 33 nqb2 output differential output pair b2. lvds interface levels. 34 qb3 output differential output pair b3. lvds interface levels. 35 nqb3 output differential output pair b3. lvds interface levels. 36 qb4 output differential output pair b4. lvds interface levels. 37 nqb4 output differential output pair b4. lvds interface levels. 38 qb5 output differential output pair b5. lvds interface levels. 39 nqb5 output differential output pair b5. lvds interface levels. 40 v ddqb power power supply pin for the channel b outputs qb[0:5]. epad gnd_epad power exposed pad of package. connect to ground. [a] pull-up (pu) and pull-down (pd) resistors are indicated in parentheses. pull-up and pull-down refers to internal input resistors. see table 5, dc input characteristics, for typical values. table 1. pin descriptions [a] number name type description
4 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet function tables table 2. selaa output amplitude selection table selaa qa output amplitude (mv) 0 350 1 (default) 500 table 3. selab output amplitude selection table selab qb output amplitude (mv) 0 350 1 (default) 500
5 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet absolute maximum ratings note: the absolute maximum ratings are stress ratings only. stresses greater than those listed below can cause permanent damage to the device. functional operation of the 8P34S2106 at absolute maximum ratings is not implied. exposure to absolute maximum rating conditions may affect device reliability . dc electrical characteristics table 4. absolute maximum ratings item rating supply voltage, v dd [a] [a] v dd denotes v dda , v ddb . 4.6v inputs, v i -0.5v to 3.6v outputs, i o continuous current surge current 10ma 15ma input sink/source, i ref 2ma maximum junction temperature, t j,max 125c storage temperature, t stg -65c to 150c esd - human body model [b] [b] according to jedec js-001-2012/jesd22-c101e. 2000v esd - charged device model [b] 1500v table 5. dc input characteristics symbol parameter test conditions minimum typical maximum units c in input capacitance 2 pf r pulldown input pull-down resistor 51 k ? r pullup input pull-up resistor 51 k ? table 6. power supply dc characteristics, v dda = v ddb = v ddqa = v ddqb = 1.8v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v ddqa, v ddqb power supply voltage 1.71 1.8 1.89 v v ddqa , v ddqb output supply voltage 1.71 1.8 1.89 v i dda + i ddb + i ddqa + i ddqb core and output supply current qa[0:5], qb[0:5] outputs terminated 100 ? between nqx, qx 500mv amplitude 300 390 ma 350mv amplitude 210 275 ma
6 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet table 7. lvcmos inputs dc characteristics, v dda = v ddb = v ddqa = v ddqb = 1.8v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v ih input high voltage selaa, selab 0.75 v dd [a] v dd [a] + 0.3 v v il input low voltage selaa, selab -0.3 0.25 v dd [a] v i ih input high current selaa, selab v in = v dd [a] = 1.89v 10 a i il input low current selaa, selab v in = 0v, v dd [a] = 1.89v -150 a [a] v dd denotes v dda , v ddb . table 8. differential inputs characteristics, v dda = v ddb = v ddqa = v ddqb = 1.8v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units i ih input high current clka, nclka clkb, nclkb v in = v dd [a] = 1.89v 150 a i il input low current clka, clkb v in = 0v, v dd [a] = 1.89v -10 a nclka, nclkb v in = 0v, v dd [a] = 1.89v -150 a vrefa, b reference voltage [b] i ref = +100a, v dd [a] = 1.8v 0.9 1.30 v [a] v dd denotes v dda , v ddb . [b] vref[a:b] specification is applicable to the ac-coupled input interfaces shown in figure 5 and figure 6 . table 9. lvds dc characteristics, v dda = v ddb = v ddqa = v ddqb = 1.8v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units ? v od v od magnitude change 50 mv ? v os v os magnitude change 50 mv
7 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet ac electrical characteristics table 10. ac electrical characteristics, v dd = 1.8v 5%, t a = -40c to 85c [a] [a] electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the d evice is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. symbol parameter test conditions minimum typical maximum units f ref input frequency 2ghz ? v/ ? t input edge rate 1.5 v/ns t pd propagation delay [b], [c] [b] measured from the differential input crossing point to the differential output crossing point. [c] input v pp = 400mv. clka to any qax, clkb to any nqbx 100 255 400 ps t sk(o) output skew [d], [e] 20 40 ps t sk(b) output bank skew [e], [f] 10 25 ps t sk(p) pulse skew [g] f ref = 100mhz 5 25 ps t sk(pp) part-to-part skew [e], [h] 200 ps t jit buffer additive phase jitter, rms; 500mv amplitude; refer to additive phase jitter f ref = 156.25mhz; integration range: 1khz ? 40mhz 60 80 fs f ref = 156.25mhz square wave, v pp = 1v; integration range: 12khz ? 20mhz 45 60 fs ? n ( ? 30m) clock single-side band phase noise ? 30mhz offset from carrier and noise floor < -160 dbc/hz t jit, sp spurious suppression, coupling between channels f qa = 491.52mhz, f qb = 61.44mhz; measured between neighboring outputs -55 db f qa = 491.52mhz, f qb = 15.36mhz; measured between neighboring outputs -65 db t r / t f output rise/ fall time 10% to 90%, outputs loaded with 100 ? 150 400 ps 20% to 80%, outputs loaded with 100 ? 90 160 ps v pp input voltage amplitude clka, clkb 0.15 1.2 v v pp_diff differential input voltage amplitude clka, clkb 0.3 2.4 v v cmr common mode input voltage [i] 1.1 v dd [j] ? ( v pp/2 )v v od differential output voltage selaa, selab = 0, outputs loaded with 100 ? 247 350 454 mv selaa, selab = 1, outputs loaded with 100 ? 350 500 650 mv v os offset voltage selaa, selab = 0 0.8 v selaa, selab = 1 0.7 v
8 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet [d] defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the differential cros s points. [e] this parameter is defined in accordance with jedec standard 65. [f] defined as skew within a bank of outputs at the same voltage and with equal load conditions. [g] output pulse skew is the absolute value of the difference of the propagation delay times: ? t plh - t phl ? . [h] defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cros s points. [i] common mode input voltage is defined as the cross-point voltage. [j] v dd denotes v dda , v ddb .
9 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase nois e is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the po wer value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the funda mental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired appli cation over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. figure 2. additive phase jitter. frequency: 156.25mhz, integration range: 12khz to 20mhz = 45fs typical as with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipme nt. the noise floor of the equipment can be higher or lower than the noise floor of the device. additive phase noise is dependent on bo th the noise floor of the input source and measurement equipment. measured using a wenzel 156.25mhz oscillator as the input source. ssb phase noise dbc/hz offset from carrier frequency (hz)
10 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet applications information recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating there should be no trace attached. vrefx the unused vrefa and vrefb pins can be left floating. we recommend that there is no trace attached.
11 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet wiring the differential input to accept single-ended levels figure 3 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be lo cated as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 1.8v and v dd = 1.8v, r1 and r2 value should be adjusted to set v 1 at 0.9v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termin ation at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be redu ced while maintaining an edge rate faster than 1v/ns. the datasheet specifies a lower differential amplitude, however this only applies t o differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utili zed for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 3. recommended schematic for wiring a differential input to accept single-ended levels
12 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet 1.8v differential clock input interface the clk /nclk accepts lvds, lvpecl and other differential signals. the differential input signal must meet both the v pp and v cmr input requirements. figure 4 to figure 6 show interface examples for the clk /nclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 4. differential input driven by an lvds driver - dc coupling figure 5. differential input driven by an lvds driver - ac coupling figure 6. differential input driven by an lvpecl driver - ac coupling
13 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full lin e of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 7 can be used with either type of output structure. figure 8 , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the output structure is current source or voltage sou rce type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verifie d for compatibility with the output. figure 7. standard lvds termination figure 8. optional lvds termination lvds driver z o ? z t z t lvds receiver lvds driver z o ? z t lvds receiver c z t 2 z t 2
14 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorpora ted on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 9 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be desi gned on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board thro ugh a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pa ttern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possibl e. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desi rable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pa d/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land patt ern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note o n the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 9. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
15 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet case temperature considerations this device supports applications in a natural convection environment which does not have any thermal conductivity through ambi ent air. the printed circuit board (pcb) is typically in a sealed enclosure without any natural or forced air flow and is kept at or bel ow a specific temperature. the device package design incorporates an exposed pad (epad) with enhanced thermal parameters which is soldered to the pcb where most of the heat escapes from the bottom exposed pad. for this type of application, it is recommended to use the junction-to-board thermal characterization parameter ? jb (psi-jb) to calculate the junction temperature (t j ) and ensure it does not exceed the maximum allowed junction temperature in the absolute maximum rating table. the junction-to-board thermal characterization parameter, ? jb, is calculated using the following equation: t j = t cb + ? jb x p d, where t j = junction temperature at steady state condition in ( o c). t cb = case temperature (bottom) at steady state condition in ( o c). ? jb = thermal characterization parameter to report the difference between junction temperature and the temperature of the board measured at the top surface of the board. p d = power dissipation (w) in desired operating configuration. the epad provides a low thermal resistance path for heat transfer to the pcb and represents the key pathway to transfer heat aw ay from the ic to the pcb. it?s critical that the connection of the exposed pad to the pcb is properly constructed to maintain the desi red ic case temperature (t cb ). a good connection ensures that temperature at the exposed pad (t cb ) and the board temperature (t b ) are relatively the same. an improper connection can lead to increased junction temperature, increased power consumption and decreased electric al performance. in addition, there could be long-term reliability issues and increased failure rate. example calculation for junction temperature (t j ): t j = t cb + ? jb x p d for the variables above, the junction temperature is equal to 106.1 o c. since this is below the maximum junction temperature of 125 o c, there are no long term reliability concerns. in addition, since the junction temperature at which the device was characterized using forced convection is 115 o c, this device can function without the degradation of the specified ac or dc parameters. package type 40 vfqfn body size (mm) 6 x 6 x 0.9 epad size (mm) 4.65 x 4.65 thermal via 4 x 4 matrix ? jb 1.5 o c/w t cb 105 o c p d 0.71w t j t cb
16 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet power considerations this section provides information on power dissipation and junction temperature for the 8P34S2106. equations and example calculations are also provided. 1. power dissipation. the following is the power dissipation for v dd = 1.8v + 5% = 1.89v, which gives worst case results. maximum current at 85c: v dd_max = 390ma. ? power_ max = v dd_max * i dd_max = 1.89v * 390ma = 737.1mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 24.6c/w per table 11 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.7371w * 24.6c/w = 103.1c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 11. thermal resistance ? ja for 40-lead vfqfn, forced convection ? ja (c/w) vs. air flow (m/s) meters per second 0 1 2 40-lead vfqfn multi-layer pcb, jedec standard test boards 24.6 21.2 19.6
17 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet package drawings figure 10. 40-lead vfqfn package outline and dimensions
18 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet package drawings, continued figure 11. 40-lead vfqfn package outline and dimensions
19 ?2016 integrated device technology, inc. october 20, 2016 8P34S2106 datasheet marking diagram ordering information table 12. ordering information part/order number marking package shipping packaging temperature 8P34S2106nlgi idt8P34S2106nlgi 40-lead vfqfn, lead-free tray -40c to 85c 8P34S2106nlgi8 idt8P34S2106nlgi tape & reel, pin 1 orientation: eia-481-c 8P34S2106nlgi/w idt8P34S2106nlgi tape & reel, pin 1 orientation: eia-481-d/e table 13. pin 1 orientation in tape and reel packaging part number suffix pin 1 orientation illustration 8 quadrant 1 (eia-481-c) /w quadrant 2 (eia-481-d/e) 1. line 1 and line 2 indicates the part number. 2. line 3: ? ?#? indicates stepping. ? ?yyww? indicates the date code (yy are the last two digits of the year, and ?ww? is a work week number that the part was assembled. ? ?$? indicates the mark code. ?
8P34S2106 datasheet 20 ?2016 integrated device technology, inc. october 20, 2016 disclaimer integrated device technology, inc. (idt) reserves the right to modify the products an d/or specifications described h erein at any time, without notice, at id t's sole discretion. performance spec- ifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without represent ation or warranty of any ki nd, whether express or imp lied, including, but not lim ited to, the suitability of idt's product s for any particular purpose, an implied warranty of merchantability, or non-infringement of the inte llectual property rights of others. this docum ent is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be rea- sonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other c ountries. other trademarks used herein are the property of idt or their respective third party owners. for datas heet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology, inc.. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com revision history revision date description of change october 20, 2016 page 1, features , added device current consumption. page 9, added additive phase jitter section. page 19, added marking diagram . updated datasheet formatting. july 28, 2016 features section - corrected phase jitter bullet spec from <50fs to 45fs. july 8, 2016 initial final datasheet.

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